On Sunday a new beta of my SystemVerilog plugin was released. It contains two critical fixes. First, it fixes a crash when renaming modules and secondly it drastically improves code completion (and performance) for sequential code.

The update automatically downloaded for all users who can choose to upgrade when appropriate.

How to rename any object in a project

The Edaphic Studio SystemVerilog plugin has a powerful feature for renaming any object across files in a project. It's an important feature that I believe you will find very useful so In this section, I wanted to show how to use it.

Having to rename an object used throughout a project can be a pain. I know from experience that many of us hesitate to do it as it takes many compile-fix-error cycles to get it right. Waiting to rename an object is especially true if the object has a generic name like "clk," "reset_n" or "i." We tend to live with old names which lead to confusion.

With the Edaphic Studio SystemVerilog plugin renaming any object, is easy to do. Just move to the definition of the object (Ctrl-B), enter rename mode (Shift-F6), change the object's name and exit rename mode (Shift-F6 again). This rename all usages of the object across the system.

_It's important to realize that this work even if you are trying to rename something generic like clk,``reset_n or i. The SystemVerilog plugin only renames usages of the chosen object by analyzing the scope and hierarchy tree to find actual usages. Rename is not a simple search-and-replace script!_

Once you get used to it, I think you will use it a lot.

It's a feature that makes coding more manageable, so I created a small video for it and a step-by-step example below.

You can try it out by using the Truss project example and following these steps:

Go to the uart_top declaration by using the search-anywhere command [double shift]; typing "uatop" and picking the uart_top class (in uart_top.v):

Optional! List all usages by using Ctrl-B:

With the cursor on uart_top enter rename mode using Shift-F6. This highlights the current variable in a red box. Rename the variable to uart_16550_top:

Exit rename mode with Shift-F6. This brings up a confirmation window (where you can optionally choose to search and update comments). Click Refactor or simply hit Enter:

Optional! Use Ctrl-B again to confirm name changes.

So renaming any object is as easy as entering rename mode (shift-F6), changing the object name and exiting rename mode (shift-F6). It's a feature I think you will find instrumental.

You can undo a rename with Ctrl-Z which reverts the name change across affected files.

Happy Coding!

Better code-completion inside sequential code

This release fixes code completion issues inside any sequential code. The problem was highlighted in issue #9. This fix will make day to day coding much better! We hope you enjoy it.

The fix was somewhat involved, so for the interested here is a more in-depth explanation:

The #9 code-completion issue forced a much needed but large optimization of the statement rule detector logic. The core issue was that just typing an identifier didn't match any specific rule as it matched many. None of these matches had enough information to say - I'm it.

When no rule matches then no code completion happens since code completion is content aware and only completes for objects in scope.

The solution was to restructure the statement detector to unify all rules that can start with an Identifier into a single master rule. SystemVerilog has a lot of rules that can do that! This change improves not only code-completion but also error messages, error recovery and overall performance.

There is a similar optimization needed for modules #8. If you find other places where code-completion doesn't automatically work, please let me know, and it will get updated. Having smart code-completion working is a high-priority issue.

Next release

The next couple of releases will continue to deal with code-completion. Focusing first on getting variable name code-completion to work reliably everywhere. The following completion improvement will be for code in module space (see #8 for details). If you find places where code-completion doesn't happen, please file issues, and I will get to them as soon as possible.

Once variable code-completion works reliably, then keyword completion will be added. This feature is a comparably simple task but still needs to smarts to only show keywords relevant to your scope.