Today I'm updating my JetBrains' based SystemVerilog Editor with a small but essential update: smart block formatting as you type. As with any upgrade, this new feature will automatically push to my users.
Before diving deeper into this feature, I'd like to ask for your help in recruiting new users! I need help getting the word out. Please consider sharing this blog post with colleagues who might be interested in trying my SystemVerilog editor out.
Looking for more users!
The SystemVerilog editor is still in beta, but it is also ready to be your real-world editor! It's in use in several projects most of them using UVM. The main reason it's staying in beta is that I'm still working with JetBrains on the licensing and marketplace solution. So new users can take advantage of this delay and get an extended trial period!
My goal with this project is to create the best SystemVerilog editor. An editor that increases productivity and fun while minimizing syntax errors and frustrations. A tool you want to use every day. In my mind, this project is starting to do that. I'd love to hear more users opinions.
To create the best editor I've been focusing on writing a built-in SystemVerilog analyzer. This analyzer operates while you type and marks syntax errors and warnings; parses module and class hierarchies; does scope based code completion; project-wide renames; navigates to any definition; formats the code and much more. It does all this without using any external tools, and of-course installs easily on any platform and automatically keeps itself up-to-date. There is a lot more information on the website.
Add to that great JetBrains editor features like search-every-where (double shift), run any command (ctrl-shift-a) and great graphical version control support, and you have a fresh new experience for writing SystemVerilog.
JetBrains' even provides excellent emacs and VIM modes to help to transition.
JetBrains' is not well known in the EDA field, but they are the company behind the official Android Studio IDE as well as PyCharm, CLion and IntelliJ. With your support I hope to turn Edaphic Studio into an IDE of with the same quality. JetBrains have a large and active user base which reflects in the quality of their editor, and it's updated regularly with new features.
So please help spread the word by sharing this blog-post or pointing engineers to the project's website: https://www.edaphic.studio
Better block handling
This updated adds automatic formatting of blocks as you type. For now, it's only for blocks (i.e. begin and end ). I wanted to release it as this is the way I'm planning to handle all paired keywords (like class/end class or module/end module). So I would appreciate feedback on this feature.
The intent is to automatically insert the closing keyword as soon as you type the opening keyword. Then when you hit enter the code is reformatted as expected and labels inserted. The labels update on any enter inside the block. Finally, the end keyword is only gets added as needed.
Together these automatic additions should minimize how much typing you need to do. I've included a small video demonstration for how it all works.
This update also includes internal fixes how parsing of macro arguments as well as minor updates for how checking of labels works.
Next feature in the works: Smart code completion for keywords
It's time for me to deal with some low hanging fruits. Features that most users expect but that I haven't implemented yet as I deemed them low-risk.
However, it's high time to implement some of the features since more complex features like compiler directives now work. The two most requested features are keyword code completion and improved highlighting.
I will start with the keyword code completion first, but instead of merely adding a long list all the SystemVerilog keywords Edaphic Studio will match possible keywords with where you are in your code. That way the list of options will stay relevant and short.
I hope to be able to introduce this feature soon.